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<a href="#define-members">Macros</a> &#124;
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<div class="title">xiomodule_l.h File Reference</div>  </div>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="mdescLeft">&#160;</td><td class="mdescRight">Defines the number of timer counters within a single hardware device.  <a href="group__iomodule__v2__2.html#gaba99b973ef1f13bf0a2716cf52ca5319">More...</a><br /></td></tr>
<tr class="separator:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22c78277a54b31ec738e72eca0662e35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga22c78277a54b31ec738e72eca0662e35">XTC_TIMER_COUNTER_OFFSET</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga22c78277a54b31ec738e72eca0662e35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each timer counter consumes 16 bytes of address space.  <a href="group__iomodule__v2__2.html#ga22c78277a54b31ec738e72eca0662e35">More...</a><br /></td></tr>
<tr class="separator:ga22c78277a54b31ec738e72eca0662e35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3154a9fc1e2fd70c0cc37772e15b907"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gad3154a9fc1e2fd70c0cc37772e15b907">XUL_RX_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:gad3154a9fc1e2fd70c0cc37772e15b907"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define the offsets from the base address for all the registers of the IO module, some registers may be optional in the hardware device.  <a href="group__iomodule__v2__2.html#gad3154a9fc1e2fd70c0cc37772e15b907">More...</a><br /></td></tr>
<tr class="separator:gad3154a9fc1e2fd70c0cc37772e15b907"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a78233dc7306487ebb9c5adebacac00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga0a78233dc7306487ebb9c5adebacac00">XUL_TX_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga0a78233dc7306487ebb9c5adebacac00"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Transmit Register - W.  <a href="group__iomodule__v2__2.html#ga0a78233dc7306487ebb9c5adebacac00">More...</a><br /></td></tr>
<tr class="separator:ga0a78233dc7306487ebb9c5adebacac00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13cc5a4dd0ee4939136579f2e8dc9ce5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga13cc5a4dd0ee4939136579f2e8dc9ce5">XUL_STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga13cc5a4dd0ee4939136579f2e8dc9ce5"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Status Register - R.  <a href="group__iomodule__v2__2.html#ga13cc5a4dd0ee4939136579f2e8dc9ce5">More...</a><br /></td></tr>
<tr class="separator:ga13cc5a4dd0ee4939136579f2e8dc9ce5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa2bc39bbb18ba649d4afbe729ee246c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaa2bc39bbb18ba649d4afbe729ee246c0">XUL_BAUDRATE_OFFSET</a>&#160;&#160;&#160;0x0000004C</td></tr>
<tr class="memdesc:gaa2bc39bbb18ba649d4afbe729ee246c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Baud Rate Register - W.  <a href="group__iomodule__v2__2.html#gaa2bc39bbb18ba649d4afbe729ee246c0">More...</a><br /></td></tr>
<tr class="separator:gaa2bc39bbb18ba649d4afbe729ee246c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2dc06911d25b46e1ddad8e2938f95b4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga2dc06911d25b46e1ddad8e2938f95b4c">XIN_IMR_OFFSET</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:ga2dc06911d25b46e1ddad8e2938f95b4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Mode Register - W.  <a href="group__iomodule__v2__2.html#ga2dc06911d25b46e1ddad8e2938f95b4c">More...</a><br /></td></tr>
<tr class="separator:ga2dc06911d25b46e1ddad8e2938f95b4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c685bb29e51f4564a7aea4d2d7fce34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga3c685bb29e51f4564a7aea4d2d7fce34">XGO_OUT_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga3c685bb29e51f4564a7aea4d2d7fce34"><td class="mdescLeft">&#160;</td><td class="mdescRight">General Purpose Output - W.  <a href="group__iomodule__v2__2.html#ga3c685bb29e51f4564a7aea4d2d7fce34">More...</a><br /></td></tr>
<tr class="separator:ga3c685bb29e51f4564a7aea4d2d7fce34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7602eedbe37417de638a1f7825f80132"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga7602eedbe37417de638a1f7825f80132">XGI_IN_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga7602eedbe37417de638a1f7825f80132"><td class="mdescLeft">&#160;</td><td class="mdescRight">General Purpose Input - R.  <a href="group__iomodule__v2__2.html#ga7602eedbe37417de638a1f7825f80132">More...</a><br /></td></tr>
<tr class="separator:ga7602eedbe37417de638a1f7825f80132"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c1ce88ba61c2e42054faaef40539556"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga4c1ce88ba61c2e42054faaef40539556">XIN_ISR_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga4c1ce88ba61c2e42054faaef40539556"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Status Register - R.  <a href="group__iomodule__v2__2.html#ga4c1ce88ba61c2e42054faaef40539556">More...</a><br /></td></tr>
<tr class="separator:ga4c1ce88ba61c2e42054faaef40539556"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35c8f39e63012c1745df6faa39fc7335"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga35c8f39e63012c1745df6faa39fc7335">XIN_IPR_OFFSET</a>&#160;&#160;&#160;0x00000034</td></tr>
<tr class="memdesc:ga35c8f39e63012c1745df6faa39fc7335"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Pending Register - R.  <a href="group__iomodule__v2__2.html#ga35c8f39e63012c1745df6faa39fc7335">More...</a><br /></td></tr>
<tr class="separator:ga35c8f39e63012c1745df6faa39fc7335"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12fbacf76cabd206d17acefd187fa7b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga12fbacf76cabd206d17acefd187fa7b4">XIN_IER_OFFSET</a>&#160;&#160;&#160;0x00000038</td></tr>
<tr class="memdesc:ga12fbacf76cabd206d17acefd187fa7b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Enable Register - W.  <a href="group__iomodule__v2__2.html#ga12fbacf76cabd206d17acefd187fa7b4">More...</a><br /></td></tr>
<tr class="separator:ga12fbacf76cabd206d17acefd187fa7b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf12b5f9e19d0d544e8df96699db615bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaf12b5f9e19d0d544e8df96699db615bd">XIN_IAR_OFFSET</a>&#160;&#160;&#160;0x0000003C</td></tr>
<tr class="memdesc:gaf12b5f9e19d0d544e8df96699db615bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Acknowledge Register - W.  <a href="group__iomodule__v2__2.html#gaf12b5f9e19d0d544e8df96699db615bd">More...</a><br /></td></tr>
<tr class="separator:gaf12b5f9e19d0d544e8df96699db615bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38a380fdcb3114c3db51524a8182c4ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga38a380fdcb3114c3db51524a8182c4ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timer Load register - W.  <a href="group__iomodule__v2__2.html#ga38a380fdcb3114c3db51524a8182c4ad">More...</a><br /></td></tr>
<tr class="separator:ga38a380fdcb3114c3db51524a8182c4ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad054cd3c12bc686f9be366e093c2f97a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gad054cd3c12bc686f9be366e093c2f97a">XTC_TCR_OFFSET</a>&#160;&#160;&#160;0x00000044</td></tr>
<tr class="memdesc:gad054cd3c12bc686f9be366e093c2f97a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timer counter register - R.  <a href="group__iomodule__v2__2.html#gad054cd3c12bc686f9be366e093c2f97a">More...</a><br /></td></tr>
<tr class="separator:gad054cd3c12bc686f9be366e093c2f97a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81c9a818cb57cf5f106cf5a3b7c3c59f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>&#160;&#160;&#160;0x00000048</td></tr>
<tr class="memdesc:ga81c9a818cb57cf5f106cf5a3b7c3c59f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timer Control register - W.  <a href="group__iomodule__v2__2.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">More...</a><br /></td></tr>
<tr class="separator:ga81c9a818cb57cf5f106cf5a3b7c3c59f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab675a4446c4ab809551ea73ad2ca962d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gab675a4446c4ab809551ea73ad2ca962d">XIN_IVAR_OFFSET</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gab675a4446c4ab809551ea73ad2ca962d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Vector Address Register, Interrupt 0 offset, present only for Fast Interrupt - W.  <a href="group__iomodule__v2__2.html#gab675a4446c4ab809551ea73ad2ca962d">More...</a><br /></td></tr>
<tr class="separator:gab675a4446c4ab809551ea73ad2ca962d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33cf5a2b5ddc5ae960235ce37cd6c32f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga33cf5a2b5ddc5ae960235ce37cd6c32f">XUL_SR_PARITY_ERROR</a>&#160;&#160;&#160;0x80</td></tr>
<tr class="memdesc:ga33cf5a2b5ddc5ae960235ce37cd6c32f"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART status register bit position masks.  <a href="group__iomodule__v2__2.html#ga33cf5a2b5ddc5ae960235ce37cd6c32f">More...</a><br /></td></tr>
<tr class="separator:ga33cf5a2b5ddc5ae960235ce37cd6c32f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef49f4399d015532ee90cda2c0045324"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaef49f4399d015532ee90cda2c0045324">XUL_SR_INTR_ENABLED</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:gaef49f4399d015532ee90cda2c0045324"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Interrupt enabled.  <a href="group__iomodule__v2__2.html#gaef49f4399d015532ee90cda2c0045324">More...</a><br /></td></tr>
<tr class="separator:gaef49f4399d015532ee90cda2c0045324"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76bf6a9a14882e45364a21693be7e920"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga76bf6a9a14882e45364a21693be7e920">XUL_SR_TX_FIFO_FULL</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga76bf6a9a14882e45364a21693be7e920"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Transmit FIFO full.  <a href="group__iomodule__v2__2.html#ga76bf6a9a14882e45364a21693be7e920">More...</a><br /></td></tr>
<tr class="separator:ga76bf6a9a14882e45364a21693be7e920"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a1722c4c799b50641831e1d092d9893"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga7a1722c4c799b50641831e1d092d9893">XUL_SR_RX_FIFO_VALID_DATA</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:ga7a1722c4c799b50641831e1d092d9893"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Data Register valid.  <a href="group__iomodule__v2__2.html#ga7a1722c4c799b50641831e1d092d9893">More...</a><br /></td></tr>
<tr class="separator:ga7a1722c4c799b50641831e1d092d9893"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9a9355e4872a6de8340af575c2aec72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaf9a9355e4872a6de8340af575c2aec72">XUL_STOP_BITS</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaf9a9355e4872a6de8340af575c2aec72"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART stop bits are fixed at 1.  <a href="group__iomodule__v2__2.html#gaf9a9355e4872a6de8340af575c2aec72">More...</a><br /></td></tr>
<tr class="separator:gaf9a9355e4872a6de8340af575c2aec72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b04347e664ae6d55ebd9d2609191767"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga3b04347e664ae6d55ebd9d2609191767">XUL_PARITY_NONE</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga3b04347e664ae6d55ebd9d2609191767"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Parity definitions.  <a href="group__iomodule__v2__2.html#ga3b04347e664ae6d55ebd9d2609191767">More...</a><br /></td></tr>
<tr class="separator:ga3b04347e664ae6d55ebd9d2609191767"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga230620599fe987b03b47e6d04a442e60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga230620599fe987b03b47e6d04a442e60">XIOModule_EnableIntr</a>(BaseAddress,  EnableMask)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + <a class="el" href="group__iomodule__v2__2.html#ga12fbacf76cabd206d17acefd187fa7b4">XIN_IER_OFFSET</a>, (EnableMask))</td></tr>
<tr class="memdesc:ga230620599fe987b03b47e6d04a442e60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable specific interrupt(s) in the interrupt controller.  <a href="group__iomodule__v2__2.html#ga230620599fe987b03b47e6d04a442e60">More...</a><br /></td></tr>
<tr class="separator:ga230620599fe987b03b47e6d04a442e60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf77d72d553f17c2696ce54e3149f0d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaaf77d72d553f17c2696ce54e3149f0d0">XIOModule_DisableIntr</a>(BaseAddress,  DisableMask)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + <a class="el" href="group__iomodule__v2__2.html#ga12fbacf76cabd206d17acefd187fa7b4">XIN_IER_OFFSET</a>, ~(DisableMask))</td></tr>
<tr class="memdesc:gaaf77d72d553f17c2696ce54e3149f0d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable specific interrupt(s) in the interrupt controller.  <a href="group__iomodule__v2__2.html#gaaf77d72d553f17c2696ce54e3149f0d0">More...</a><br /></td></tr>
<tr class="separator:gaaf77d72d553f17c2696ce54e3149f0d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac3f5aa29d205f6221a017a04712c65f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gac3f5aa29d205f6221a017a04712c65f0">XIOModule_AckIntr</a>(BaseAddress,  AckMask)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + <a class="el" href="group__iomodule__v2__2.html#gaf12b5f9e19d0d544e8df96699db615bd">XIN_IAR_OFFSET</a>, (AckMask))</td></tr>
<tr class="memdesc:gac3f5aa29d205f6221a017a04712c65f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Acknowledge specific interrupt(s) in the interrupt controller.  <a href="group__iomodule__v2__2.html#gac3f5aa29d205f6221a017a04712c65f0">More...</a><br /></td></tr>
<tr class="separator:gac3f5aa29d205f6221a017a04712c65f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga128f261df0c50d6e1b090e2a9e9d1874"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga128f261df0c50d6e1b090e2a9e9d1874">XIOModule_GetIntrStatus</a>(BaseAddress)&#160;&#160;&#160;(XIomodule_In32((BaseAddress) + <a class="el" href="group__iomodule__v2__2.html#ga35c8f39e63012c1745df6faa39fc7335">XIN_IPR_OFFSET</a>))</td></tr>
<tr class="memdesc:ga128f261df0c50d6e1b090e2a9e9d1874"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the interrupt status from the interrupt controller which indicates which interrupts are active and enabled.  <a href="group__iomodule__v2__2.html#ga128f261df0c50d6e1b090e2a9e9d1874">More...</a><br /></td></tr>
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<tr class="memitem:ga313c2576e159fd472cb0b25b7a395837"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga313c2576e159fd472cb0b25b7a395837">XIOModule_GetStatusReg</a>(BaseAddress)&#160;&#160;&#160;XIomodule_In32((BaseAddress) + <a class="el" href="group__iomodule__v2__2.html#ga13cc5a4dd0ee4939136579f2e8dc9ce5">XUL_STATUS_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:ga313c2576e159fd472cb0b25b7a395837"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the contents of the UART status register.  <a href="group__iomodule__v2__2.html#ga313c2576e159fd472cb0b25b7a395837">More...</a><br /></td></tr>
<tr class="separator:ga313c2576e159fd472cb0b25b7a395837"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9c5e48a02c0aba03cb1d8d7583b37f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gad9c5e48a02c0aba03cb1d8d7583b37f6">XIOModule_IsReceiveEmpty</a>(BaseAddress)</td></tr>
<tr class="memdesc:gad9c5e48a02c0aba03cb1d8d7583b37f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check to see if the UART receiver has data.  <a href="group__iomodule__v2__2.html#gad9c5e48a02c0aba03cb1d8d7583b37f6">More...</a><br /></td></tr>
<tr class="separator:gad9c5e48a02c0aba03cb1d8d7583b37f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93c23372164e627f79da9488ea43161a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga93c23372164e627f79da9488ea43161a">XIOModule_IsTransmitFull</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga93c23372164e627f79da9488ea43161a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check to see if the transmitter is full.  <a href="group__iomodule__v2__2.html#ga93c23372164e627f79da9488ea43161a">More...</a><br /></td></tr>
<tr class="separator:ga93c23372164e627f79da9488ea43161a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga829c77e3efe996211599f9a2a6bb4890"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga829c77e3efe996211599f9a2a6bb4890">XIOModule_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;XIomodule_Out32((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga829c77e3efe996211599f9a2a6bb4890"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write a value to a GPO register.  <a href="group__iomodule__v2__2.html#ga829c77e3efe996211599f9a2a6bb4890">More...</a><br /></td></tr>
<tr class="separator:ga829c77e3efe996211599f9a2a6bb4890"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eaff234e65f369a870fca3b92215df4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga4eaff234e65f369a870fca3b92215df4">XIOModule_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XIomodule_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga4eaff234e65f369a870fca3b92215df4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a value from a GPI register.  <a href="group__iomodule__v2__2.html#ga4eaff234e65f369a870fca3b92215df4">More...</a><br /></td></tr>
<tr class="separator:ga4eaff234e65f369a870fca3b92215df4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader"></div></td></tr>
<tr class="memitem:gafb21e053e2c12734dfadd0affbbbc313"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gafb21e053e2c12734dfadd0affbbbc313">XGPI_DEVICE_COUNT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gafb21e053e2c12734dfadd0affbbbc313"><td class="mdescLeft">&#160;</td><td class="mdescRight">Defines the number of GPI and GPO within a single hardware device.  <a href="group__iomodule__v2__2.html#gafb21e053e2c12734dfadd0affbbbc313">More...</a><br /></td></tr>
<tr class="separator:gafb21e053e2c12734dfadd0affbbbc313"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9569489084c770e95974e4592e425b66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga9569489084c770e95974e4592e425b66">XGPI_CHAN_OFFSET</a>&#160;&#160;&#160;0x00004</td></tr>
<tr class="memdesc:ga9569489084c770e95974e4592e425b66"><td class="mdescLeft">&#160;</td><td class="mdescRight">The following constants describe the offset of each GPI and GPO channel's data from the base address.  <a href="group__iomodule__v2__2.html#ga9569489084c770e95974e4592e425b66">More...</a><br /></td></tr>
<tr class="separator:ga9569489084c770e95974e4592e425b66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77dbab318178a69596d6cab5c3971dc9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga77dbab318178a69596d6cab5c3971dc9">XIN_IOMODULE_GPI_4_INTERRUPT_INTR</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:ga77dbab318178a69596d6cab5c3971dc9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt register bit position masks.  <a href="group__iomodule__v2__2.html#ga77dbab318178a69596d6cab5c3971dc9">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Control Status Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Control Status Register bit masks Used to configure the timer counter device. </p>
</div></td></tr>
<tr class="memitem:gaa7cbbacf96f3f51bcd12d5826b03e620"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaa7cbbacf96f3f51bcd12d5826b03e620"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the timer.  <a href="group__iomodule__v2__2.html#gaa7cbbacf96f3f51bcd12d5826b03e620">More...</a><br /></td></tr>
<tr class="separator:gaa7cbbacf96f3f51bcd12d5826b03e620"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab06d844c7a245c7be88a63f3559bbd46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gab06d844c7a245c7be88a63f3559bbd46">XTC_CSR_AUTO_RELOAD_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gab06d844c7a245c7be88a63f3559bbd46"><td class="mdescLeft">&#160;</td><td class="mdescRight">In compare mode, configures the timer reload from the Load Register.  <a href="group__iomodule__v2__2.html#gab06d844c7a245c7be88a63f3559bbd46">More...</a><br /></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga77e0649e78c817c27b628b6713c12451"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga77e0649e78c817c27b628b6713c12451">XIOModule_SendByte</a> (u32 BaseAddress, u8 Data)</td></tr>
<tr class="memdesc:ga77e0649e78c817c27b628b6713c12451"><td class="mdescLeft">&#160;</td><td class="mdescRight">This functions sends a single byte using the UART.  <a href="group__iomodule__v2__2.html#ga77e0649e78c817c27b628b6713c12451">More...</a><br /></td></tr>
<tr class="separator:ga77e0649e78c817c27b628b6713c12451"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1784b245813307028ba028246e39606"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaf1784b245813307028ba028246e39606">XIOModule_RecvByte</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:gaf1784b245813307028ba028246e39606"><td class="mdescLeft">&#160;</td><td class="mdescRight">This functions receives a single byte using the UART.  <a href="group__iomodule__v2__2.html#gaf1784b245813307028ba028246e39606">More...</a><br /></td></tr>
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<tr class="memitem:ga2e47bfda481c3ceab60d758f049758ef"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga2e47bfda481c3ceab60d758f049758ef">XIOModule_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr class="memdesc:ga2e47bfda481c3ceab60d758f049758ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is the interrupt handler for the driver interface provided in this file when there can be no argument passed to the handler.  <a href="group__iomodule__v2__2.html#ga2e47bfda481c3ceab60d758f049758ef">More...</a><br /></td></tr>
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<tr class="memitem:gaaf27e1820d586ec1c487078d03854944"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#gaaf27e1820d586ec1c487078d03854944">XIOModule_SetIntrSvcOption</a> (u32 BaseAddress, int Option)</td></tr>
<tr class="memdesc:gaaf27e1820d586ec1c487078d03854944"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs.  <a href="group__iomodule__v2__2.html#gaaf27e1820d586ec1c487078d03854944">More...</a><br /></td></tr>
<tr class="separator:gaaf27e1820d586ec1c487078d03854944"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3985a47858bc59f526d475536811a393"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iomodule__v2__2.html#ga3985a47858bc59f526d475536811a393">XIOModule_RegisterHandler</a> (u32 BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)</td></tr>
<tr class="memdesc:ga3985a47858bc59f526d475536811a393"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a handler function for a specific interrupt ID.  <a href="group__iomodule__v2__2.html#ga3985a47858bc59f526d475536811a393">More...</a><br /></td></tr>
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